Method and apparatus for anisotropic etching

ABSTRACT

In anisotropic etching of the substrates, ultra-thin and conformable layers of materials can be used to passivate sidewalls of the etched features. Such a sidewall passivation layer may be a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. Alternatively, the sidewall passivation layer may be an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD s layer deposition can be carried out in a pulsing regime alternating with sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition is carried out continuously, while etch or sputtering turns on in a pulsing regime. Alternatively, SAM deposition and etch or sputtering may be carried out continuously. Both types of suggested passivation materials give advantage over state-of-the-art methods in ability to carefully control thickness and uniformity of the layers, thus enable anisotropic etching process for high aspect ratio nanosize features.

This application claims the benefit of U.S. Provisional Application No. 60/933,989, filed Jun. 9, 2007 and PCT/US2008/006355, filed May 17, 2008. This application is a continuation-in-part of International Application No. PCT/US2008/006355, filed May 17, 2008, which claims the benefit of Provisional Application No. 60/933,989, filed Jun. 9, 2007.

FIELD

This invention relates to a method for etching a substrate in an anisotropic manner. In particular, although, not exclusively, the method and apparatus relate to anisotropic etching of nanosize features with high aspect ratios in a substrate.

BACKGROUND

A method of anisotropic etching of silicon by cyclic etch and deposition steps in a plasma environment is known as “Bosch process” from German patent DE4241045, issued 5 Dec. 1992 and U.S. Pat. No. 5,501,893, issued 26 Mar. 1996, titled “Method of anisotropically etching silicon”. This anisotropic plasma etching has been applied to other materials such as Ge, SiGe and GasAs.

When etching high-aspect-ratio silicon features using the “Bosch process” (DRIE--deep reactive ion etching), researchers found that there is a maximum achievable aspect ratio, “critical aspect ratio”, of an etched silicon trench. At this critical aspect ratio, the apparent etch rate defined as the total depth etched divided by the total elapsed time no longer monotonically decreases as the aspect ratio increases, but abruptly drops to zero.

Junghoon Yeom, et al, in the paper titled “Maximum achievable aspect ratio in deep reactive ion etching of silicon due to aspect ratio dependent transport and the microloading effect”, J. Vac. Sci. Technol. B, Vol. 23, No. 6, November/December 2005, 2319-2329, proposed a theoretical model to predict the critical aspect ratio and reveal its causal mechanism. The model considers aspect ratio dependent transport mechanisms specific to each of the reactant species in the three subprocesses of a time-multiplexed etch cycle: deposition of a fluorocarbon passivation layer, etching of the fluorocarbon polymer at the bottom of the trench, and the subsequent etching of the underlying silicon. The model predicts that the critical aspect ratio is defined by the aspect ratio at which the polymer etch rate equals the product of the deposition rate and the set time ratio between the deposition and etching phases for the time-multiplexed process. Several DRIE experiments were performed to qualitatively validate the model. Both model simulations and experimental results demonstrate that the magnitude of the critical aspect ratio primarily depends on (i) the relative flux of neutral species at the trench opening, i.e., the microloading effect, and (ii) aspect ratio dependent transport of ions during the polymer etching subprocess of a DRIE cycle.

This result means that thick sidewall passivation layers limit “critical aspect ratio” achievable with DRIE process. This effect becomes especially important for nanosize structures where high aspect ratio feature etch requires extremely thin passivation layers.

C. Craigie et al, in the paper titled, “Polymer thickness effects on Bosch etch profiles”, J. Vac. Sci. Technol. B 20.6., November-December 2002, 2229-2232, reported thick polymer films developing on Bosch etched features as a result of both long deposition times and high C₄F₈ flow rates. Polymer builds up on the sidewalls of trenches. Where polymer thickness is a significant proportion of the trench width, the incident ion flux is restricted. Narrow trenches converge more rapidly than wide ones, as a greater proportion of the width is obscured.

The regular thickness of sidewall polymer passivation layers in state-of-the-art DRIE process is larger than 1000 Å, as reported by J. Reimers et al in the Danish technical Institute Report titled “Fabrication of a Microfluidic System for Magnetic Separation using Deep Reactive Ion Etching”, 2004. In some cases such sidewall polymers are reported in micrometer ranges, for example in abovementioned paper of C. Craigie. Alcatel Vacuum Technology at the website, www.adizen.com (M. Puech, et al, “A Novel Plasma Release Process and Super High Aspect Ratio Process using ICP Etching got MEMS”) proposed so called “SHARP” process (Super High Aspect Ratio Process), consisting of inserting a specific passivation removal step by oxygen plasma. This passivation removal process is 5 times faster than traditional SF₆-based process step. It was demonstrated that this special passivation layer removal step, performed prior to etching step, allowed to achieve aspect ratio etch as high as 60.

Martin Walker from Oxford Technology in the paper titled “Comparison of Bosch and cryogenic processes for patterning high aspect ratio features in silicon”, published in Proceedings of SPIE, Volume 4407, MEMS Design, Fabrication, Characterization, and Packaging, April 2001, pp. 89-99, describes another problem with Bosch passivation process, when it is applied to high aspect ratio feature etch: As the ratio of depth to width increases, so the attack on the sidewalls due to ion bombardment becomes less. This can result in build-up of polymer, resulting in negative profiles if it occurs at the top of the hole, or the formation of grass when it occurs at the bottom etched surface.

The same author describes so called “cryo” process as an alternative to Bosch process. Just as for the Bosch process, this technique also uses SF₆ to provide fluorine radicals for silicon etching. The silicon is removed in the form of SiF₄, which is volatile. The main difference is in the mechanism of sidewall passivation and mask protection. Rather than using a fluorocarbon polymer, this process relies on forming a blocking layer of oxide/fluoride (SiO_(x)E_(y)) on the sidewalls (around 10-20 nm thick), together with cryogenic temperatures inhibiting attack on this layer by the fluorine radicals. The low temperature operation also assists in reducing the etch rate of the mask material, which is normally either photoresist or silicon dioxide. The attack on these materials by free radical fluorine is chemical in nature and is sensitive to temperature, with the etch rate dropping rapidly at cryogenic temperatures. The low temperature can have a bad effect on some organic materials, causing cracking. This is more severe for thicker photoresists than for thin layers. As a rough guideline, layers of resist used for this process should not be more than 1.5 μm thick, to avoid the hazard of cracking.

Yi Zhao et al, in the paper titled “Creating Silicon nanostructures with Controllable Sidewall Profiles by Using Fluorine-Enhanced Oxide Passivation”, The 10th International Conference on Miniaturized Systems for Chemistry and Life Sciences (uTAS2006), Nov. 5-9, 2006, Tokyo, Japan, suggested an alternative to the “cryo” process by alternating reactive ion etching and air exposure: During plasma etching, F being adsorbed on the surface breaks preexisting Si—O bonds and form Si—F group, thus forming a SiO_(x)F_(y)layer. When exposed to the coexistence of oxygen and moisture, the Si—F groups are quickly replaced by Si—OH groups from the water vapor ambient due to the similar ionicity. The Si—OH groups bridge and form layers of oxide. The oxide continues to grow due to field assisted Mott-Cabrera mechanism. The fluorine-enhanced oxide layer postpones the attack of the sidewalls during the following brief plasma etching. The sidewall passivation is thus enabled. Obviously, control of sidewall passivation layer thickness and uniformity is very problematic with this method.

Suk Won Yu has used dielectric etch preventing spacer deposited on the sidewall of the etched feature in KR 10-2006-0030717. Unfortunately, due to the chosen deposition method such spacer is quite thick and non-uniform along the length of the sidewall feature, as it clearly seen from the patent's text and the drawing. Mr. Yu does not teach how to get uniformly deposited sidewall passivation layer, which will be thin enough and uniform enough for nano-sized features with high aspect ratio.

SUMMARY

We suggest a method of anositropic etching of the substrates, where ultra-thin and conformable layers of materials are used to passivate sidewalls of the etched features.

According to an exemplary embodiment such sidewall passivation layer is a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase.

According to another exemplary embodiment such sidewall passivation layer is an inorganic-based material deposited using Atomic Layer Deposition (ALD) method.

SAM or ALD layers deposition can be carried out in a pulsing regime alternating with an etching or sputtering processes using process gasses with or without plasma. Alternatively, a SAM deposition process is carried out continuously, while an etch or sputtering process turns on in a pulsing regime. Alternatively, a SAM deposition process and etch or sputtering processes are carried out continuously.

Both types of suggested passivation materials give advantages over state-of-the-art methods in ability to carefully control thickness and uniformity of the layers, and thus enable extending achievable high aspect ratio and narrow nanosize feature anisotropic etching process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic representation of Self-assembled Monolayer (SAM). Deposition of these layers is self-limiting (deposition stops when entire surface is filled with one layer of molecules), thus thickness of this layer is always equal to the one molecular length (practical thickness range is 0.5-3 nm) and uniformity of deposited layer is 100%.

FIG. 2 is a schematic which shows the status after the SAM or ALD-material deposition step: substrate 1 is covered with patterned photoresist 2, and then SAM or ALD-material layer 3 deposited on top of both, photoresist 4 and exposed substrate material 5.

FIG. 3 is a schematic which shows the status after the first etching or sputtering step: SAM or ALD-material layer is etched or sputtered from the horizontal areas of the photoresist 4 and substrate material 5, but remains on the sidewall of the photoresist feature 6

FIG. 4 is a schematic which shows the status after the main etching step: substrate material is etched into the bulk 7. This will end the first cycle. The same 3 steps then repeated certain amount of time to get the desired etch depth

FIG. 5 is a schematic which shows the status after the second cycle.

FIG. 6 is a schematic which shows the status after completion of the entire etch process: substrate feature is etched to the desired depth, sidewalls are still protected with SAM or ALD-material layer deposition

FIG. 7 is a schematic which shows the status after optional SAM or ALD-material layer stripping from the sidewall of the feature.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

As a preface to the detailed description, it should be noted that, as used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents, unless the context clearly dictates otherwise.

The present invention solves the problems associated with thickness and uniformity of sidewall passivation layers and enables successful high-aspect ratio anisotropic etch of micro and, especially, nanostructures.

In accordance with the first embodiment of the present invention, passivation polymer is deposited from the vapor phase in the form of self-assembled monolayer (SAM).

Self-assembled monolayers (FIG. 1) are arrays of aligned molecules, which have so called, a “head group”, used to attach molecule to the substrate using covalent or other bonding, organic “backbone”, and a “tail” group, which may have different properties (hydrophobic, hydrophilic, etc. Deposition process is self-limiting; it stops once the entire surface is covered with SAM, since the second layer of SAM can not be attached to the first. It means that SAM can not be accumulated on the sidewall and the thickness of such passivation layer on the sidewalls of the etched feature is the same through entire etch process. Uniformity of the deposition is excellent, since thickness is equal to the height of a single molecule (0.5-3 nm). FIG. 1 shows schematic representation of SAM, where ordered and self-aligned molecules are formed on the surface.

SAM can be easily removed (sputtered) from the bottom of the feature using low energy ion bombardment, but SAM protects sidewalls of the feature from being etched, thus provides high anisotropy of the etch process.

Though self-assembled monolayers are very thin, they proved to be useful masking materials for wet etch. Buchwalter et al. in the patent application US20030211341, filed Nov. 13, 2003, and titled “Self-assembled Monolayer Etch barrier for Indium-Tin-Oxide Useful in manufacturing Thin Film Transistor-Liquid Crystal display, used n-alkylsilanes monolayers as an etch masks for ITO (indium-titanium-oxide) etch by wet solution of 3.5% aqueous oxalic acid during 5 min (which etched 500 A of unmasked ITO). M. Geissler et al in the paper titled “Selective wet-etching of microcontact-printed Cu substrates with control over etch profile”, Microelectronic Engineering, v.67-68, N1, June 2003, p. 326-332, used SAMs as an etch masks for Cu etch, and T. Komeda et al in the paper titled, “Octadecyltrichlorosilane self-assembled monolayer islands as a self-patterned-mask for HF etching of SiO2 on Si.”, J. Vac. Sci & Tech., A16, N3, May 1998, p. 1680-1685, used Octadecyltrichlorosilane (OTS) SAM as an etch mask for Hydrofluoric acid etch of SiO2 material.

Utilization of self assembled monolayers as an etch masks for dry (plasma) etch has been more problematic, because of the selectivity issues: these layers are too thin and get etched fast, which does not allow receiving significant etch depth of unmasked regions of the substrate. Yet, it has been reported some resistance of OTS (Octadecyltrichlorosilane) against C1₂ plasma with 400 W microwave power at low pressures (2 mTorr), as shown in the paper of M. J. Lercel et al, titled “Pattern transfer of electron beam modified self-assembled monolayers for high-resolution lithography”, J. Vac. Sci & Tech., B13, N3, May 1995, p. 1139-1143. The layer retained hydrophobicity after 8 s exposure to this plasma conditions.

The current invention declares that Self-assembled Monolayers (SAMs) deposited on the sidewalls of the masking material and etched feature (trench, hole, etc.), which are not experiencing direct ion bombardment from Reactive Ion Etch plasma, are able to protect them from etch. Moreover, parts of SAM passivation layer damaged by grazing ion collisions or ion backscattering from the bottom of the trench can be “healed” with consecutive SAM deposition steps. Again, thickness of the “healed” layer still will not exceed one monolayer. Thus, SAMs can be successfully used as a sidewall passivation layers in anisotropic etch.

SAM deposition can be accomplished using a wide variety of organic precursors. Some examples of them are: Octadecyltrichlorosilane (OTS), Octyltrichlorosilane (OTCS), Dodecyltrichlorosilane (DDTCS), dimethyldichlorosilane (DDMS), tridecafluoro-1,1,2,2-tetrahydrooctyltrichlorosilane (,FOTS), heptadecafluoro-1,1,2,2-tetrahydrodecyltrichlorosilane (FDTS), (tridecafluoro-1,1,2,2,-tetrahydrooctyl)trisdimethylamino silane (PF8TAS), (heptadecafluoro-1,1,2,2,-tetrahydrodecyl)tris-dimethylamino silane (PF10TAS). Some precursors, like chlorosilanes, require, catalyst (water vapour or ozone gas), and others, like aminosilanes, can be used without catalyst.

Referring to FIG. 2, substrate 1 is patterned with etch mask 2 using one of the known patterning techniques. Etch mask can be, for example, photoresist material.

In accordance with the first embodiment, during the first process step entire surface of the substrate is covered with SAM passivation layer 3, which includes mask (photoresist) horizontal surfaces 4, sidewalls of the patterned feature 6, and exposed areas of the substrate 5.

In accordance with another embodiment of the present invention thin inorganic films are used as a sidewall passivation layers. Such films can be deposited using well-known Atomic Layer Deposition techniques, wherein two vapors or gases are sequentially injected into the vacuum chamber and pumped from it, which builds a very conformal material over substrate surface, layer-by-layer. Very thin ALD deposited films can provide necessary passivation of sidewalls against etching species and, since ALD films are very thin, can be easily sputtered by directional ion beam of the biased plasma during etching step of the process.

Example of such passivation film is aluminum oxide, which can be grown by sequential introduction to the chamber Trimethylaluminum (TMA) and water vapor or ozone gas. Another example is titanium oxide, which can be grown by sequential introduction to the chamber titanium tetrachloride and water vapor. ALD deposition of these films at low temperatures (room to 100 C) can be done at rates about 1-5 Å/cycle.

During the second process step, shown on FIG. 3, plasma ions, created by known reactive ion etching methods (RIE, ICP, TCP, etc.) in the presence of gasses (for example, Ar, He, etc.), directed towards the substrate surface, sputter or etch SAM or ALD-type passivation layer from the horizontal surfaces 4 of the mask material 2 and exposed area 5 of substrate material 1. Since during the biased plasma process the ions are moving vertically downward, they can make only grazing collisions with the self-assembled monolayer on the sidewalls resulting in removal of just the SAM or ALD-type passivation layer at the base of the feature (horizontal surfaces 5), leaving this layer on the sidewalls 6 intact. Passivation layer 6 protects sidewall of the mask material 2 from being eroded during following sputtering and etching steps, thus helps to preserve critical dimension of the etched feature and enabling high aspect ratio etching process.

In accordance with another embodiment of the present invention removal of SAM passivation layer from the bottom of the etched feature is done UV exposure, preferably in an ambient of ozone or oxygen, or moisture. SAMs are efficiently etched by UV exposure in the presence of ozone. UV exposure can be implemented by providing a UV lamp or Laser and directing a light beams or collimated beam into the chamber toward the substrate material, preferably normal to the substrate surface.

The third process step is an etching of exposed area 5 of the substrate material 1, which creates (increases) feature depth 7 (FIG. 4). Again, the etching can be done any known dry etching process (RIE, ICP, TCP or other types of plasma etch process) with set of gasses appropriate for etching of specific substrate material. For example, for Si etch one can chose perfluorinated gases SF₆, for oxides etch it is CHF₃ or CF₄.

In accordance with another embodiment of the present invention etching of substrate material is performed with non-plasma etching means, for example, XeF₂ etch for Si or Ge, or anhydrous vapor HF etch for oxides.

The cycle of the described three process steps is repeated again, and at the end of the second cycle of the process (FIG. 6), sidewalls of mask material and the etched feature are covered with SAM or ALD-type passivation layer 6 protecting etched feature dimension.

The etch cycles include the above three process steps (passivation layer deposition, passivation layer etch from the horizontal surfaces, and etch of the substrate material) continues further until the substrate is etched to the desired depth (FIG. 7).

Remaining SAM can be etched from the sidewalls of the etched feature using oxygen plasma or ozone, or special wet stripping process (FIG. 8).

Remaining ALD-type passivation layer can be etched from the sidewalls of the etched feature using vapor or liquid etching processes. For example, ALD oxide can be etched using HF vapor or liquid processes (FIG. 8).

In accordance with another embodiment of the present invention the second and the third process steps are performed simultaneously, that is, removal of SAM or ALD-type passivation layer from the bottom of the etched feature is done simultaneously with material etch, using the same process. In this case parameters of plasma etching process are modified to provide some directionality (anisotropy) of etch. Usually it is done by providing some bias to the plasma to increase ion directionality towards the substrate surface.

In accordance with another embodiment of the present invention SAM or ALD-type layer deposition is carried out without interruption, but sputtering or etching it from the bottom of the etched feature, and etching of substrate material—are performed in pulsing or cycling regime. SAM or ALD-precursor vapors are injected or flown into the vacuum chamber all the time, but etching gasses are injected or flown into the chamber during short periods with certain interruption time for deposition only process. This way SAM or ALD-type layer deposition process may create more continuous layer on the surface and better protect it from etching.

In accordance with another embodiment of the present invention all 3 steps—passivation layer deposition, sputtering or etching it from the bottom of the etched feature, and etching of substrate material—are performed simultaneously, without interruptions or cycling: SAM or ALD-precursor vapors are injected or flown into the vacuum chamber along with the gases for etching. Varying specific process parameters (namely, partial pressures and plasma bias) allow dynamic equilibrium between growth of passivation layers, their sputtering from horizontal surfaces, and effective material etch to be achieved.

According to a further aspect of the present invention, there is provided an apparatus for performing the method described above, comprising a chamber, means for depositing a passivation layer and means for etching a substrate and passivation layer.

The means for etching the substrate and passivation layer may be provided by supplying one or more reactive gases or vapours to the chamber. For Si material etching it can be SF₆ ClF₃ BrF₅ XeF₂, etc. For oxide material etching it can be CHF₃, CF₄ or other etching gases or anhydrous HF vapor. For SAM or ALD-type passivation layer sputtering can be achieved using biased plasma of Ar, He or other non-reactive gases.

Specific embodiments may include further supplying RF energy (inductively or capacitively coupled via electrodes) or microwave energy to a plasma in the chamber.

The means for depositing a passivation layer in the form of SAM or ALD-type layers may be provided by injecting vapours to the chamber by evaporation of liquid or solid chemical precursor, stored in a precursor supply cylinder or bottle. Alternatively, vapours can be carried from the precursor supply bottle with a help of carrier gas, for example, nitrogen.

EXAMPLE ONE

For the purpose of illustration of possible implementations of the invention, here is a specific embodiment of anisotropic etch of Si material.

Step-1: Deposition step: SAM passivation layer is deposited by flowing vapor of (heptadecafluoro-1,1,2,2,-tetrahydrodecyl)tris-dimethylamino silane into the chamber at a partial pressure of 100-500 mTorr for 5-30 seconds, and then evacuating chamber to the base pressure.

Step-2: SAM etching from the bottom of the trench step: ICP plasma of SF₆ with addition of Ar (for example, ratio 2:1) and small plasma bias (electrode power 5-20W). 1-3 seconds of exposure to this plasma conditions should be enough to etch any SAM layer from horizontal surfaces.

Step-3: Si material etch step: 5-10 seconds of SF₆ (100-200 sccm flow range)/Ar (30-80 sccm flow range) plasma, ICP coil power 600-900 W, bias 5-10 W.

Steps 1-3 are repeated until desired feature depth is reached.

EXAMPLE TWO

For the purpose of illustration of possible implementations of the invention, here is a specific embodiment of Si material anisotropic etch.

Deposition step: SAM passivation layer is deposited during entire etch process by flowing vapor of (heptadecafluoro-1,1,2,2,-tetrahydrodecyl)tris-dimethylamino silane into the chamber at a partial pressure of 100-500 mTorr

SAM etching from the bottom of the trench step and Si etching are carried out in a pulsing regime, 1-3 s ON, 3-5 s OFF. Parameters of this step: SF6 (100-200 sccm flow range)/Ar (30-80 sccm flow range) plasma, ICP power 600-900 W, bias 5-10 W.

Process per above is continued until desired feature depth is reached.

EXAMPLE THREE

For the purpose of illustration of possible implementations of the invention, here is a specific embodiment of Si material anisotropic etch.

Step-1: Deposition step: Al₂O₃ passivation layer is deposited by flowing vapor of Tetramethylaluminum (TMA) into the chamber for 0.5-1 s at a partial pressure of 50-200 mtorr, then evacuating the chamber to the base pressure, purging chamber with Nitrogen for 1-2 s, then injecting ozone gas for 0.5-1 s, evacuating chamber to base pressure and purging it with Nitrogen for 1-2 s. Then, by repeating this cycle 5 times, 7-10 Åof Al₂O₃ is grown on substrate surface.

Step-2: Al₂O₃ sputtering from the bottom of the trench step: ICP plasma of SF₆ with addition of Ar (for example, ratio 2:1) and small plasma bias (electrode power 5-20 W). 1-3 seconds of exposure to this plasma conditions should be enough to sputter 10 Åof Al₂O₃ from horizontal surfaces.

Step-3: Si material etch step: 5-10 seconds of SF₆ (100-200 sccm flow range)/Ar (30-80 sccm flow range) plasma, ICP coil power 600-900 W, bias 5-10 W.

Steps 1-3 are repeated until desired feature depth is reached.

EXAMPLE FOUR

For the purpose of illustration of possible implementations of the invention, here is a specific embodiment of Si material anisotropic etch.

Step-1: Deposition step: SAM passivation layer is deposited by flowing vapours of (heptadecafluoro-1,1,2,2,-tetrahydrodecyl)tris-dimethylamino silane into the chamber at a partial pressure of 100-500 mTorr for 5-30 s, and then evacuating chamber to the base pressure.

Step-2: SAM etching from the bottom of the trench step: RIE plasma of Ar (partial pressure 200-500 mTorr) and small plasma bias (electrode power 10-20 W). 1-3 seconds of exposure to this plasma conditions should be enough to etch any SAM layer from horizontal surfaces.

Step-3: Si material etch step: 5-10 seconds of XeF₂ (1.4 Torr partial pressure)

Steps 1-3 are repeated until desired feature depth is reached.

EXAMPLE FIVE

For the purpose of illustration of possible implementations of the invention, here is a specific embodiment of Quartz material anisotropic etch.

Step-1: Deposition step: Al₂O₃ passivation layer is deposited by flowing vapor of Tetramethylaluminum (TMA) into the chamber for 0.5-1 s at a partial pressure of 50-200 mTorr, then evacuating chamber to the base pressure, purging chamber with Nitrogen for 1-2 s, then injecting ozone gas for 0.5-1 s, evacuating chamber to base pressure and purging it with Nitrogen for 1-2 s. Then, by repeating this cycle 5 times, 7-10 Åof Al₂O₃ is grown on substrate surface.

Step-2: Al₂O₃ sputtering from the bottom of the trench step: RIE plasma of Ar (200-500 mTorr partial pressure) and small plasma bias (electrode power 10-20 W). 1-3 seconds of exposure to this plasma conditions should be enough to sputter 10 Å of Al₂O₃ from horizontal surfaces.

Step-3: Silicon oxide material etch step: 5-10 seconds of anhydrous HF vapor HF/CH₃OH) mixture 3-8 Torr partial pressure, 25:1 ratio).

Steps 1-3 are repeated until desired feature depth is reached. 

We claim:
 1. A method of treating a substrate material or film present on a material surface comprising: (a) depositing a passivation layer on the surfaces of an etched feature and masking material as a self-assembled monolayer (SAM), wherein a thickness of the passivation layer on a sidewall of the etched feature is less than 3 nm, wherein the passivation layer is a self-assembled monolayer (SAM), (b) removing the passivation layer from horizontal areas of the mask material and bottom of the etched feature, and (c) etching the substrate material to increase the depth of the etched feature, while the passivation layer on the sidewall protects the sidewall of the etched feature from being etched.
 2. A method according to claim 1, wherein the SAM passivation layer is a silane compound.
 3. A method according to claim 2, wherein the silane compound is alkylsilane or aminosilane.
 4. A method according to claim 1, wherein step b) is done using ion bombardment.
 5. A method according to claim 1, wherein step b) is done using UV light exposure.
 6. A method according to claim 1, wherein step c) is done using a plasma etch process.
 7. A method according to claim 1, wherein step c) is done using HF vapors or anhydrous HF vapors mixed with alcohol vapors.
 8. A method according to claim 1, wherein step c) is done using exposure to XeF₂ vapor.
 9. A method of treating a substrate material or film present on a material surface comprising: (a) depositing a passivation layer on the surfaces of an etched feature and masking material as a self-assembled monolayer (SAM) or by using an Atomic Layer Deposition process, wherein a thickness of the passivation layer on a sidewall of the etched feature is less than 10 nm, (b) removing the passivation layer from horizontal areas of the mask material and bottom of the etched feature, and (c) etching the substrate material to increase the depth of the etched feature, while the passivation layer on the sidewall protects the sidewall of the etched feature from being etched, wherein b) and c) are performed simultaneously.
 10. A method according to claim 9, wherein all 3 steps—a), b) and c)—are done simultaneously until a desired etch depth achieved.
 11. The method of claim 9, wherein the passivation layer is a self-assembled monolayer (SAM).
 12. A method according to claim 9, wherein said passivation layer is a layer deposited using an Atomic Layer Deposition process (ALD-type layer).
 13. A method according to claim 12, wherein said ALD-type layer is a metal oxide, like aluminum oxide, titanium oxide, or silicon oxide, silicon nitride, silicon oxynitride, or metal oxynitride.
 14. A method of treating a substrate material or film present on a material surface comprising: (a) depositing a passivation layer on the surfaces of an etched feature and masking material as a self-assembled monolayer (SAM) or by using an Atomic Layer Deposition process, wherein a thickness of the passivation layer on a sidewall of the etched feature is less than 10 nm, (b) removing the passivation layer from horizontal areas of the mask material and bottom of the etched feature, and (c) etching the substrate material to increase the depth of the etched feature, while the passivation layer on the sidewall protects the sidewall of the etched feature from being etched, wherein step a) is performed continuously, and steps b) and c) are done in a pulsing regime, until a desired etch depth achieved.
 15. The method of claim 14, wherein the passivation layer is a self-assembled monolayer (SAM).
 16. A method according to claim 14, wherein said passivation layer is a layer deposited using an Atomic Layer Deposition process (ALD-type layer).
 17. A method according to claim 16, wherein said ALD-type layer is a metal oxide, like aluminum oxide, titanium oxide, or silicon oxide, silicon nitride, silicon oxynitride, or metal oxynitride. 